Vector concatenation(连接) operator¶
What is vector concatenation operator?¶
Part selection was used to select portions of a vector. The concatenation operator {a,b,c}
is used to create larger vectors by concatenating smaller portions of a vector together.
Verilog | |
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Concatenation needs to know the width of every component (or how would you know the length of the result?). Thus, {1, 2, 3}
is illegal and results in the error message: unsized constants are not allowed in concatenations
.
The concatenation operator can be used on both the left and right sides of assignments.
- 关注第四行语法
assign out[15:0] = {in[7:0], in[15:8]};
Practice¶
Problem statement¶
Given several input vectors, concatenate them together then split them up into several output vectors. There are six 5-bit input vectors: a, b, c, d, e, and f, for a total of 30 bits of input. There are four 8-bit output vectors: w, x, y, and z, for 32 bits of output. The output should be a concatenation of the input vectors followed by two
1
bits:
Verilog | |
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