Adder 2¶
Problem statement¶
In this exercise, you will create a circuit with two levels of hierarchy. Your
top_module
will instantiate two copies ofadd16
(provided), each of which will instantiate 16 copies ofadd1
(which you must write). Thus, you must write two modules:top_module
andadd1
.Like module_add, you are given a module
add16
that performs a 16-bit addition. You must instantiate two of them to create a 32-bit adder. Oneadd16
module computes the lower 16 bits of the addition result, while the secondadd16
module computes the upper 16 bits of the result. Your 32-bit adder does not need to handle carry-in (assume 0) or carry-out (ignored).Connect the
add16
modules together as shown in the diagram below. The provided moduleadd16
has the following declaration:
Verilog Within each
add16
, 16 full adders (moduleadd1
, not provided) are instantiated to actually perform the addition. You must write the full adder module that has the following declaration:
Verilog Recall that a full adder computes the sum and carry-out of a+b+cin.
In summary, there are three modules in this design:
top_module
— Your top-level module that contains two of...add16
, provided — A 16-bit adder module that is composed of 16 of...add1
— A 1-bit full adder module.
Verilog | |
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