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And gate

Problem statement

This circuit now has three wires (a, b, and out). Wires a and b already have values driven onto them by the input ports. But wire out currently is not driven by anything. Write an assign statement that drives out with the AND of signals a and b.

Verilog
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module top_module( 
    input a, 
    input b, 
    output out );

endmodule

Solution

Verilog
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module top_module( 
    input a, 
    input b, 
    output out );
    assign out=a&b;
endmodule
  • "&"是按位与
  • "&&"是逻辑与